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publication number 21610 revision d amendment 8 issue date november 11, 2009 am29f032b am29f032b cover sheet data sheet the following document contains info rmation on spansion memory products. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansi on product. any changes that have been made are the result of normal data sheet improvem ent and are noted in the document revision summary. for more information please contact your local sales office for additional information about spansion memory solutions.
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data sheet this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 21610 rev: d amendment: 8 issue date: november 11, 2009 am29f032b 32 megabit (4 m x 8-bit) cmos 5.0 volt-only, uniform sector flash memory distinctive characteristics 5.0 v 10%, single power supply operation ? minimizes system level power requirements manufactured on 0.32 m process technology high performance ? access times as fast as 70 ns low power consumption ? 30 ma typical active read current ? 30 ma typical program/erase current ? <1 a typical standby current (standard access time to active mode) flexible sector architecture ? 64 uniform sectors of 64 kbytes each ? any combination of sectors can be erased. ? supports full chip erase ? group sector protection: ? a hardware method of locking sector groups to prevent any program or erase operations within that sector group ? temporary sector group unprotect allows code changes in previously locked sectors embedded algorithms ? embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors ? embedded program algorithm automatically writes and verifies bytes at specified addresses minimum 1,000,000 write/erase cycles guaranteed 20-year data retention at 125 c ? reliable operation for the life of the system package options ? 40-pin tsop ? 44-pin so compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard ? superior inadvertent write protection data# polling and toggle bits ? provides a software method of detecting program or erase cycle completion ready/busy output (ry/by#) ? provides a hardware method for detecting program or erase cycle completion erase suspend/resume ? suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation hardware reset pin (reset#) ? resets internal state machine to the read mode
2 am29f032b 21610d8 november 11, 2009 data sheet general description the am29f032b is a 32 mbit, 5.0 volt-only flash memory organized as 4,194,304 bytes of 8 bits each. the 4 mbytes of data are divided into 64 sectors of 64 kbytes each for flexible er ase capability. the 8 bits of data appear on dq0?dq7. the am29f032b is offered in 40-pin tsop and 44-pin so packages. the am29f032b is manufactured using amd?s 0.32 m process technology. this device is designed to be pro- grammed in-system with the standard system 5.0 volt v cc supply. a 12.0 volt v pp is not required for program or erase operations. the device can also be pro- grammed in standard eprom programmers. the standard device offers access times of 70 and 90 ns, allowing high-speed microprocessors to operate without wait states. to eliminate bus contention, the device has separate chip enable (ce#), write enable (we#), and output enable (oe#) controls. the device is entirely command set compatible with the jedec single-power-supply flash standard. com- mands are written to the command register using stan- dard microprocessor write timings. register contents serve as input to an internal state machine that con- trols the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 volt flash or eprom devices. the device is programmed by executing the program command sequence. this invokes the embedded pro- gram algorithm?an internal algorithm that automati- cally times the program pulse widths and verifies proper cell margin. the device is erased by executing the erase command sequence. this invokes the em- bedded erase algorithm?an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. a sector is typically erased and verified within one second. the device is erased when shipped from the factory. the hardware sector group protection feature disables both program and erase operations in any combination of the eight sector groups of memory. a sector group consists of four adjacent sectors. the erase suspend feature enables the system to put erase on hold for any period of time to read data from, or program data to, a sector that is not being erased. true background erase can thus be achieved. the device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automati- cally inhibits write operations during power transitions. the host system can detect whether a program or erase cycle is complete by using the ry/by# pin, the dq7 (data# polling) or dq6 (toggle) status bits. after a program or erase cycle has been completed, the de- vice automatically returns to the read mode. a hardware reset# pin term inates any operation in progress. the internal state machine is reset to the read mode. the reset# pin may be tied to the sys- tem reset circuitry. therefore, if a system reset occurs during either an embedded program or embedded erase algorithm, the device is automatically reset to the read mode. this enables the system?s microprocessor to read the boot-up firmware from the flash memory. amd?s flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the bytes are programmed one byte at a time using the programming mechanism of hot electron injection.
november 11, 2009 21610d8 am29f032b 3 data sheet table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . 7 device bus operations . . . . . . . . . . . . . . . . . . . . . 8 table 1. am29f032b device bus operations .................................. 8 requirements for reading array data ..................................... 8 writing commands/command sequences .............................. 8 program and erase operation status ...................................... 9 standby mode .......................................................................... 9 reset#: hardware reset pin ................................................. 9 output disable mode................................................................ 9 table 2. am29f032b sector address table................................... 10 autoselect mode..................................................................... 11 table 3. am29f032b autoselect codes ......................................... 11 sector group protection/unprotection.................................... 12 table 4. sector group addresses................................................... 12 temporary sector group unprotect ....................................... 12 figure 1. temporary sector group unprotect operation................ 12 hardware data protection ...................................................... 13 low vcc write inhibit..................................................................... 13 write pulse ?glitch? protection........................................................ 13 logical inhibit .................................................................................. 13 power-up write inhibit .................................................................... 13 command definitions . . . . . . . . . . . . . . . . . . . . . 13 reading array data ................................................................ 13 reset command..................................................................... 13 autoselect command sequence ............................................ 14 byte program command sequence....................................... 14 chip erase command sequence ........................................... 14 figure 2. program operation .......................................................... 15 sector erase command sequence ........................................ 15 erase suspend/erase resume commands........................... 15 figure 3. erase operation............................................................... 16 table 5. am29f032b command definitions................................... 17 write operation status . . . . . . . . . . . . . . . . . . . . 18 dq7: data# polling................................................................. 18 figure 4. data# polling algorithm ................................................... 18 dq6: toggle bit i .................................................................... 19 dq2: toggle bit ii ................................................................... 19 reading toggle bits dq6/dq2............................................... 19 dq5: exceeded timing limits ................................................ 20 dq3: sector erase timer ....................................................... 20 figure 5. toggle bit algorithm........................................................ 20 table 6. write operation status..................................................... 21 absolute maximum ratings. . . . . . . . . . . . . . . . . 22 figure 6. maximum negative overshoot waveform ...................... 22 figure 7. maximum positive overshoot waveform........................ 22 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23 ttl/nmos compatible .......................................................... 23 cmos compatible.................................................................. 23 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. test setup...................................................................... 24 table 7. test specifications ........................................................... 24 key to switching waveforms . . . . . . . . . . . . . . . 24 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25 read-only operations............................................................. 25 figure 9. read operation timings ................................................. 25 hardware reset (reset#) .................................................... 26 figure 10. reset# timings .......................................................... 26 write (erase/program) operations ......................................... 27 figure 11. program operation timings.......................................... 28 figure 12. chip/sector erase operation timings .......................... 29 figure 13. data# polling timings (during embedded algorithms). 30 figure 14. toggle bit timings (during embedded algorithms)...... 30 figure 15. dq2 vs. dq6................................................................. 31 temporary sector unprotect .................................................. 31 figure 16. temporary sector group unprotect timings ................ 31 write (erase/program) operations?alternate ce# controlled writes .................................................................... 32 figure 17. alternate ce# controlled write operation timings ...... 33 erase and programming performance . . . . . . . 34 latchup characteristic . . . . . . . . . . . . . . . . . . . . 34 tsop and so pin capacitance . . . . . . . . . . . . . 34 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 35 so 044?44-pin small outline package.................................. 35 ts 040?40-pin standard thin small outline package........... 36 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 37
4 am29f032b 21610d8 november 11, 2009 data sheet product selector guide note: see ?ac characteristics? for full specifications. block diagram family part number am29f032b speed options v cc = 5.0 v 5% -75 v cc = 5.0 v 10% -90 max access time, ns (t acc )7090 max ce# access time, ns (t ce )7090 max oe# access time, ns (t oe )4040 input/output buffers x-decoder y-decoder chip enable output enable erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 ? dq7 sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a21
november 11, 2009 21610d8 am29f032b 5 data sheet connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a19 a18 a17 a16 a15 a14 a13 a12 ce# v cc nc reset# a11 a10 a9 a8 a7 a6 a5 a4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a20 a21 we# oe# ry/by# dq7 dq6 dq5 dq4 v cc v ss v ss dq3 dq2 dq1 dq0 a0 a1 a2 a3 40-pin standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc reset# a11 a10 a9 a8 a7 a6 a5 a4 nc nc a3 a2 a1 a0 dq0 dq1 dq2 dq3 v ss v ss 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 v cc ce# a12 a13 a14 a15 a16 a17 a18 a19 nc nc a20 a21 we# oe# ry/by# dq7 dq6 dq5 dq4 v cc so
6 am29f032b 21610d8 november 11, 2009 data sheet pin configuration a0?a21 = 22 addresses dq0?dq7 = 8 data inputs/outputs ce# = chip enable we# = write enable oe# = output enable reset# = hardware rese t pin, active low ry/by# = ready/busy output v cc = +5.0 v single power supply (see product selector guide for device speed ratings and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 22 8 dq0?dq7 a0?a21 ce# oe# we# reset# ry/by#
november 11, 2009 21610d8 am29f032b 7 data sheet ordering information standard products amd standard products are available in several packages and operating ranges. the order num ber (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be support- ed in volume for this device. consult the local amd sales of- fice to confirm availability of specific valid combinations and to check on newly released combinations. am29f032b -75 e f temperature range i = industrial (?40 c to +85 c) e = extended (?55 c to +125 c) f = industrial (?40 c to +85 c) with pb-free package k = extended (?55 c to +125 c) with pb-free package package type e = 40-pin thin small outline package (tsop) standard pinout (ts 040) s = 44-pin small outline package (so 044) speed option see product selector guide and valid combinations device number/description am29f032b 32 megabit (4 m x 8-bit) cmos 5.0 volt-only sector erase flash memory 5.0 v read, program, and erase valid combinations AM29F032B-75 ei, ef, si, sf am29f032b-90 ei, ee, ef, ek si, se, sf, sk
8 am29f032b 21610d8 november 11, 2009 data sheet device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. the appropriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29f032b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = don?t care, d in = data in, d out = data out, a in = address in note: see the sections sector group protection and tem porary sector unprotect for more information. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? on page 13 for more infor- mation. refer to the ac read operations table for tim- ing specifications and to figure 9, on page 25 for the timing waveforms. i cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sec- tors, or the entire device. the sector address tables indicate the address space that each sector occupies. a ?sector address? consists of the address bits re- quired to uniquely select a sector. see the ?writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid reg- ister command sequences. writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data.? sec- tion for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes th e autoselect command se- quence, the device enters the autoselect mode. the system can then read autose lect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? on page 11 and ?autoselect command sequence? on page 14 sections for more information. i cc2 in the ?dc characteristics? on page 23 table rep- resents the active current specification for the write mode. the ? ?ac characteristics? on page 25 section operation ce# oe# we# reset# a0?a21 dq0?dq7 read l l h h a in d out write l h l h a in d in cmos standby v cc 0.5 v x x v cc 0.5 v x high-z ttl standby h x x h x high-z output disable l h h h x high-z hardware reset x x x l x high-z temporary sector unprotect (see note) xxx v id a in d in
november 11, 2009 21610d8 am29f032b 9 data sheet contains timing specificat ion tables and timing dia- grams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. the erase resume command is valid only during the erase suspend mode.refer to ?erase suspend/erase resume com- mands? on page 15 for more information, and to each ?ac characteristics? on page 25 section for timing dia- grams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the oe# input. the device enters the cmos standby mode when ce# and reset# pins are both held at v cc 0.5 v. (note that this is a more restricted voltage range than v ih .) the device enters the ttl standby mode when ce# and reset# pins are both held at v ih . the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the re- set# pin is driven low. refer to the next section, ?re- set#: hardware reset pin? . if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in dc characteristics tables, represents the standby current specification. reset#: hardware reset pin the reset# pin provides a hardware meth od of reset- ting the device to readin g array data. when the system drives the reset# pin low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v il , the device enters the ttl standby mode; if reset# is held at v ss 0.5 v, the device enters the cmos standby mode. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase oper- ation, the ry/by# pin remains a ?0? (busy) until the in- ternal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is comp lete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the ?ac characteristics? on page 25 tables for reset# parameters and timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state.
10 am29f032b 21610d8 november 11, 2009 data sheet table 2. am29f032b sector address table (sheet 1 of 2) sector a21 a20 a19 a18 a17 a16 sector size address range sa0 0 0 0 0 0 0 64k 000000h?00ffffh sa1 0 0 0 0 0 1 64k 010000h?01ffffh sa2 0 0 0 0 1 0 64k 020000h?02ffffh sa3 0 0 0 0 1 1 64k 030000h?03ffffh sa4 0 0 0 1 0 0 64k 040000h?04ffffh sa5 0 0 0 1 0 1 64k 050000h?05ffffh sa6 0 0 0 1 1 0 64k 060000h?06ffffh sa7 0 0 0 1 1 1 64k 070000h?07ffffh sa8 0 0 1 0 0 0 64k 080000h?08ffffh sa9 0 0 1 0 0 1 64k 090000h?09ffffh sa10 0 0 1 0 1 0 64k 0a0000h?0affffh sa11 0 0 1 0 1 1 64k 0b0000h?0bffffh sa12 0 0 1 1 0 0 64k 0c0000h?0cffffh sa13 0 0 1 1 0 1 64k 0d0000h?0dffffh sa14 0 0 1 1 1 0 64k 0e0000h?0effffh sa15 0 0 1 1 1 1 64k 0f0000h?0fffffh sa16 0 1 0 0 0 0 64k 100000h?10ffffh sa17 0 1 0 0 0 1 64k 110000h?11ffffh sa18 0 1 0 0 1 0 64k 120000h?12ffffh sa19 0 1 0 0 1 1 64k 130000h?13ffffh sa20 0 1 0 1 0 0 64k 140000h?14ffffh sa21 0 1 0 1 0 1 64k 150000h?15ffffh sa22 0 1 0 1 1 0 64k 160000h?16ffffh sa23 0 1 0 1 1 1 64k 170000h?17ffffh sa24 0 1 1 0 0 0 64k 180000h?18ffffh sa25 0 1 1 0 0 1 64k 190000h?19ffffh sa26 0 1 1 0 1 0 64k 1a0000h?1affffh sa27 0 1 1 0 1 1 64k 1b0000h?1bffffh sa28 0 1 1 1 0 0 64k 1c0000h?1cffffh sa29 0 1 1 1 0 1 64k 1d0000h?1dffffh sa30 0 1 1 1 1 0 64k 1e0000h?1effffh sa31 0 1 1 1 1 1 64k 1f0000h?1fffffh sa32 1 0 0 0 0 0 64k 200000h?20ffffh sa33 1 0 0 0 0 1 64k 210000h?21ffffh sa34 1 0 0 0 1 0 64k 220000h?22ffffh sa35 1 0 0 0 1 1 64k 230000h?23ffffh sa36 1 0 0 1 0 0 64k 240000h?24ffffh sa37 1 0 0 1 0 1 64k 250000h?25ffffh sa38 1 0 0 1 1 0 64k 260000h?26ffffh sa39 1 0 0 1 1 1 64k 270000h?27ffffh sa40 1 0 1 0 0 0 64k 280000h?28ffffh sa41 1 0 1 0 0 1 64k 290000h?29ffffh sa42 1 0 1 0 1 0 64k 2a0000h?2affffh sa43 1 0 1 0 1 1 64k 2b0000h?2bffffh
november 11, 2009 21610d8 am29f032b 11 data sheet note: all sectors are 64 kbytes in size. autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector group protection verifica- tion, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its corresponding programming algo- rithm. however, the autoselect codes can also be accessed in-syste m through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in ta b l e 3 . in addition, when verifying sector group pro- tection, the sector group address must appear on the appropriate highest order address bits (see ta bl e 4 o n page 12 ). ta b l e 3 also shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 5 on page 17 . this method does not require v id on an address line. refer to the autoselect command sequence section for more information. table 3. am29f032b autoselect codes note: identifier codes for manufacturer and device ids exhibit odd parity with dq7 defined as the parity bit. sa44 1 0 1 1 0 0 64k 2c0000h?2cffffh sa45 1 0 1 1 0 1 64k 2d0000h?2dffffh sa46 1 0 1 1 1 0 64k 2e0000h?2effffh sa47 1 0 1 1 1 1 64k 2f0000h?2fffffh sa48 1 1 0 0 0 0 64k 300000h?30ffffh sa49 1 1 0 0 0 1 64k 310000h?31ffffh sa50 1 1 0 0 1 0 64k 320000h?32ffffh sa51 1 1 0 0 1 1 64k 330000h?33ffffh sa52 1 1 0 1 0 0 64k 340000h?34ffffh sa53 1 1 0 1 0 1 64k 350000h?35ffffh sa54 1 1 0 1 1 0 64k 360000h?36ffffh sa55 1 1 0 1 1 1 64k 370000h?37ffffh sa56 1 1 1 0 0 0 64k 380000h?38ffffh sa57 1 1 1 0 0 1 64k 390000h?39ffffh sa58 1 1 1 0 1 0 64k 3a0000h?3affffh sa59 1 1 1 0 1 1 64k 3b0000h?3bffffh sa60 1 1 1 1 0 0 64k 3c0000h?3cffffh sa61 1 1 1 1 0 1 64k 3d0000h?3dffffh sa62 1 1 1 1 1 0 64k 3e0000h?3effffh sa63 1 1 1 1 1 1 64k 3f0000h?3fffffh table 2. am29f032b sector address table (sheet 2 of 2) sector a21 a20 a19 a18 a17 a16 sector size address range description a21-a18 a17-a10 a9 a8-a7 a6 a5-a2 a1 a0 identifier code on dq7-dq0 manufacturer id : amd x x v id xv il xv il v il 01h device id: am29f032b x x v id xv il xv il v ih 41h sector group protection verification sector group address xv id xv il xv ih v il 01h (protected) 00h (unprotected)
12 am29f032b 21610d8 november 11, 2009 data sheet sector group protection/unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. each sector group consists of four adjacent sectors. ta b l e 4 shows how the sectors are grouped, and the address range that each sector group con- tains. the hardware sector group unprotection feature re-enables both program and erase operations in pre- viously protected sector groups. sector group protection/ unprotection must be imple- mented using programming equipment. the proce- dure requires a high voltage (v id ) on address pin a9 and the control pins. details on this method are pro- vided in a supplement, publication number 22184. contact an amd representative to obtain a copy of the appropriate document. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and pro- tecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. con- tact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see ?autoselect mode? on page 11 for details. table 4. sector group addresses temporary sector group unprotect this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to v id (11.5 v ? 12.5 v). dur- ing this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algorithm, and figure 16 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation sector group a21 a20 a19 a18 sectors sga0 0 0 0 0 sa0 ? sa3 sga1 0 0 0 1 sa4 ? sa7 sga2 0 0 1 0 sa8 ? sa11 sga3 0 0 1 1 sa12 ? sa15 sga4 0 1 0 0 sa16 ? sa19 sga5 0 1 0 1 sa20 ? sa23 sga6 0 1 1 0 sa24 ? sa27 sga7 0 1 1 1 sa28 ? sa31 sga8 1 0 0 0 sa32?sa35 sga9 1 0 0 1 sa36?sa39 sga10 1 0 1 0 sa40?sa43 sga11 1 0 1 1 sa44?sa47 sga12 1 1 0 0 sa48?sa51 sga13 1 1 0 1 sa52?sa55 sga14 1 1 1 0 sa56?sa59 sga15 1 1 1 1 sa60?sa63 start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected. 2. all previously protected se ctor groups are protected once again.
november 11, 2009 21610d8 am29f032b 13 data sheet hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko (see dc characteristics for voltage levels), the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all inter- nal program/erase circuits are disabled. under this condition the device resets to the read mode. subse- quent writes are ignored until the v cc level is greater than v lko . the system must ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be at v il while oe# is at v ih . power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the im- proper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in ?ac characteristics? on page 25 . reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? on page 15 for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if dq5 goes high, or while in the autoselect mode. see ?reset command? , next. see also ?requirements for reading array data? in the ?device bus operations? section for more informa- tion. the read operations table provides the read pa- rameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an aut oselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend).
14 am29f032b 21610d8 november 11, 2009 data sheet autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom program- mers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufac- turer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refer to table 2 on page 10 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is in itiated by writing two un- lock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verify the pro- grammed cell margin. table 5 on page 17 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. see table 6 on page 21 for informa- tion on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program- ming operation. the program command sequence should be reinitiated once the device has reset to read- ing array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1?. chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. ta bl e 5 o n page 17 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately ter- minates the operation. the chip erase command se- quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. the erase resume command is valid only during the erase suspend mode. see ?erase suspend/erase resume commands? on page 15 for information on these status bits. when the embedded erase algo- rithm is complete, the device returns to reading array data and addresses are no longer latched. figure 3, on page 16 illustrates the algorithm for the erase operation. see figure 3, on page 16 for parame- ters, and to the figure 12, on page 29 for timing wave- forms.
november 11, 2009 21610d8 am29f032b 15 data sheet note: see table 5 for program command sequence. figure 2. program operation sector erase co mmand sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. two addi- tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 5 on page 17 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see ?dq3: sector erase timer? on page 20 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase operation immediately terminates the op- eration. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. the erase resume command is valid only during the erase suspend mode. see ?erase sus- pend/erase resume commands? on page 15 for infor- mation on these status bits. figure 3, on page 16 illustrates the algorithm for the erase operation. see figure 3, on page 16 for parame- ters, and to the figure 12, on page 29 for timing wave- forms. erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- dresses are ?don?t-cares? when writing the erase sus- pend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately ter- start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
16 am29f032b 21610d8 november 11, 2009 data sheet minates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sec- tors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. the erase resume command is valid only during the erase suspend mode. see ?erase suspend/erase re- sume commands? on page 15 for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program oper- ation. see ?erase suspend/erase resume com- mands? on page 15 for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see ?autoselect command sequence? on page 14 for more information. the system must write the erase resume command (address bits are ?don?t care?) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. notes: 1. see the appropriate command definitions table for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 3. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
november 11, 2009 21610d8 am29f032b 17 data sheet command definitions table 5. am29f032b command definitions legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a16 select a unique sector. sga = address of the sector group to be verified. address bits a21?a18 select a unique sector group. notes: 1. see table 1 on page 8 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a21?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading array data when device is in the autoselect mode, or if dq5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector group and 01h for a protected sector grou p.see ?autoselect command sequence ? for more information. 9. the system may read and program in non-erasing sectors, or enter the autosel ect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) cycles bus cycles (notes 2?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id 4 555 aa 2aa 55 555 90 x01 41 sector group protect verify (note 8) 4 555 aa 2aa 55 555 90 sga x02 xx00 xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 9) 1 xxx b0 erase resume (note 10) 1 xxx 30
18 am29f032b 21610d8 november 11, 2009 data sheet write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, dq7, and ry/by#. table 6 on page 21 and the following sub- sections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pr ogram address falls within a protected sector, data# polling on dq7 is active for ap- proximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase al- gorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to ?1?; prior to this, the device outputs the ?complement,? or ?0.? the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading arra y data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. the data# poll- ing timings (during embedded algorithms) figure in the ?ac characteristics? section illustrates this. table 6 on page 21 shows the outputs for data# polling on dq7. figure 4 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 4. data# polling algorithm
november 11, 2009 21610d8 am29f032b 19 data sheet ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 6 shows the outputs for ry/by#. the timing dia- grams for read, reset, program, and erase shows the relationship of ry/by# to other signals. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cy cles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycl es.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is acti vely erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on ?dq7: data# polling?). if a program address falls within a protected sector, dq6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. the write operation status table shows the outputs for toggle bit i on dq6. refer to figure 5 for the toggle bit algorithm, and to the toggle bit timings figure in the ?ac characteristics? section for the timing diagram. the dq2 vs. dq6 figure shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on ?dq2: toggle bit ii?. dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 6 on page 22 to com- pare outputs for dq2 and dq6. figure 5, on page 20 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? ex- plains the algorithm. see al so the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graph- ical form. reading toggle bits dq6/dq2 refer to figure 5, on page 20 for the following discus- sion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase oper- ation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and
20 am29f032b 21610d8 november 11, 2009 data sheet the system must write the reset command to return to reading array data. the remaining scenar io is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 5 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified intern al pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has ex- ceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if addi- tional sectors are selected for erasure, the entire time- out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from ?0? to ?1.? the system may ignore dq3 if the system can guarantee that the time between ad- ditional sector erase commands will always be less than 50 s. see also ?sector erase command se- quence? on page 15 . after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is ?1?, the internally controlled erase cycle has be- gun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been ac- cepted. table 6 on page 21 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to ?1?. see text. figure 5. toggle bit algorithm (notes 1, 2) (note 1)
november 11, 2009 21610d8 am29f032b 21 data sheet table 6. write operation status notes: 1. dq7 and dq2 require a valid address when reading status in formation. refer to the appropriate subsection for further details. 2. dq5 switches to ?1? when an embedded program or embedde d erase operation has exceeded the maximum timing limits. see ?dq5: exceeded timing limits? for more information. operation dq7 (note 1) dq6 dq5 (note 2) dq3 dq2 (note 1) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
22 am29f032b 21610d8 november 11, 2009 data sheet absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . .?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . .?55 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?2.0 v to 7.0 v a9, oe#, reset# (note 2) . . . . . ?2.0 v to 13.0 v all other pins (note 1) . . . . . . . . . . ?2.0 v to 7.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may overshoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on a9, oe#, reset# pins is ? 0.5v. during voltage transitions, a9, oe#, reset# pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 6. maximum dc input voltage on a9, oe#, and reset# is 13.0 v which may overshoot to 13.5 v for periods up to 20 ns. 3. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. stresses greater than those list ed in this section may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not im plied. exposure of the device to absolute maximum rating conditions for extended periods may affect de- vice reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . .?40 c to +85 c extended (e) devices ambient temperature (t a ) . . . . . . . .?55 c to +125 c v cc supply voltages v cc for 5% devices . . . . . . . . . . .+4.75 v to +5.25 v v cc for 10% devices . . . . . . . . . .+4.50 v to +5.50 v operating ranges define thos e limits between which the functionality of the device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
november 11, 2009 21610d8 am29f032b 23 data sheet dc characteristics ttl/nmos compatible cmos compatible notes for dc characteristics (both tables): 1. the i cc current is typically less than 1 ma/mhz, with oe# at v ih . 2. i cc active while embedded program or embedded erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max, a9 = 12.0 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc read current (note 1) ce# = v il, oe# = v ih 30 40 ma i cc2 v cc write current (notes 2, 3) ce# = v il, oe# = v ih 40 60 ma i cc3 v cc standby current (ce# controlled) ce# = v ih , reset# = v ih 0.4 1.0 ma i cc4 v cc standby current (reset# controlled) v cc = v cc max, reset# = v il 0.4 1.0 ma v il input low level ?0.5 0.8 v v ih input high level 2.0 v cc + 0.5 v v id voltage for autoselect and sector protect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh output high level i oh = ?2.5 ma v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v parameter symbol parameter description test description min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max, a9 = 12.0 v 50 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc read current (note 1) ce# = v il, oe# = v ih 30 40 ma i cc2 v cc write current (notes 2, 3) ce# = v il, oe# = v ih 30 40 ma i cc3 v cc standby current (ce# controlled) ce# = v cc 0.5 v, reset# = v cc 0.5 v 15a i cc4 v cc standby current (reset# controlled) reset# = v ss 0.5 v 1 5 a v il input low level ?0.5 0.8 v v ih input high level 0.7x v cc v cc + 0.3 v v id voltage for autoselect and sector protect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 12 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ? 0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
24 am29f032b 21610d8 november 11, 2009 data sheet test conditions table 7. test specifications key to switching waveforms 2.7 k c l 6.2 k 5.0 v device under te s t figure 8. test setup note: diodes are in3064 or equivalent test condition -75 all others unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 20 ns input pulse leve ls 0.0?3.0 0.45?2.4 v input timing measurement reference levels 1.5 0.8 v output timing measurement reference levels 1.5 2.0 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
november 11, 2009 21610d8 am29f032b 25 data sheet ac characteristics read-only operations notes: 1. not 100% tested. 2. refer to figure 8 and table 7 for test specifications. parameter symbol parameter descrip tion test setup speed options unit jedec std -75 -90 t avav t rc read cycle time (note 1) min 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 90 ns t elqv t ce chip enable to output delay oe# = v il max 70 90 ns t glqv t oe output enable to output delay max 40 40 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ehqz t df chip enable to output high z (note 1) max 20 20 ns t ghqz t df output enable to output high z (note 1) max 20 20 ns t axqx t oh output hold time from addresses ce# or oe# whichever occurs first min 0 ns t ready reset# pin low to read mode (note 1) max 20 s t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh figure 9. read operation timings
26 am29f032b 21610d8 november 11, 2009 data sheet ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 10. reset# timings
november 11, 2009 21610d8 am29f032b 27 data sheet ac characteristics write (erase/program) operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter parameter description speed options unit jedec std -75 -90 t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 40 45 ns t dvwh t ds data setup time min 40 45 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recover time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 40 45 ns t whwl t wph write pulse width high min 20 ns t whwh1 t whwh1 byte programming operation (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec max 8 sec t vcs v cc set up time (note 1) min 50 s t busy we# to ry/by# valid max 40 40 ns
28 am29f032b 21610d8 november 11, 2009 data sheet ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa note: pa = program address, pd = program data, d out is the true data at the program address. figure 11. program operation timings
november 11, 2009 21610d8 am29f032b 29 data sheet ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va ry/by# t rb t busy note: sa = sector address. va = valid address for reading status data. figure 12. chip/sector erase operation timings
30 am29f032b 21610d8 november 11, 2009 data sheet ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle. figure 13. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows firs t two status cycle after command sequence, last status read cy cle, and array data read cycle. figure 14. toggle bit timings (during embedded algorithms)
november 11, 2009 21610d8 am29f032b 31 data sheet ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing note: the system may use oe# or ce# to toggle dq2 and dq6. dq 2 toggles only when read at an address within the erase-suspended sector. figure 15. dq2 vs. dq6 reset# t vidr 12 v 0 or 5 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 or 5 v figure 16. temporary sector group unprotect timings
32 am29f032b 21610d8 november 11, 2009 data sheet ac characteristics write (erase/program) operations? alternate ce# controlled writes notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter symbol parameter description speed options unit jedec std -75 -90 t avav t wc write cycle time (note 1) min 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 40 45 ns t dveh t ds data setup time min 40 45 ns t ehdx t dh address hold time min 0 ns t ghel t ghel read recover time before write min 0 ns t wlel t ws ce# setup time min 0 ns t ehwh t wh ce# hold time min 0 ns t eleh t cp write pulse width min 40 45 ns t ehel t cph write pulse width high min 20 ns t whwh1 t whwh1 byte programming operation (note 2) typ 7 s t whwh2 t whwh2 sector erase operation (note 2) typ 1 sec max 8 sec
november 11, 2009 21610d8 am29f032b 33 data sheet ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. pa = program address, pd = program data, sa = sect or address, dq7# = comple ment of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. figure 17. alternate ce# controlled write operation timings
34 am29f032b 21610d8 november 11, 2009 data sheet erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 5.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 4.5 v, 1,000,000 cycles (4.75 v for -75). 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if th e maximum byte program time given is exceeded, only then does the device set dq5 = 1. see the section on dq5 for further information. 4. in the pre-programming step of the embedded erase al gorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the f our-bus-cycle sequence for programming. see table 5 for further information on command definitions. 6. the device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. latchup characteristic note: includes all pins except v cc . test conditions: v cc = 5.0 volt, one pin at a time. tsop and so pi n capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 1 8 sec excludes 00h programming prior to erasure (note 4) chip erase time 64 sec byte programming time 7 300 s excludes system-level overhead (note 5) chip programming time (note 3) 28.8 86.4 sec description min max input voltage with respect to v ss on i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test conditions min max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
november 11, 2009 21610d8 am29f032b 35 data sheet physical dimensions so 044?44-pin small outline package dwg rev ac; 10/99
36 am29f032b 21610d8 november 11, 2009 data sheet physical dimensions ts 040?40-pin standard thin small outline package dwg rev aa; 10/99
november 11, 2009 21610d8 am29f032b 37 data sheet revision summary revision a (june 1998) initial release. revision b (july 1998) distinctive characteristics changed typical active read current to 30 ma to match dc characteristics table. operating ranges corrected temperature range descriptions to ?ambient.? revision c (january 1999) distinctive characteristics added 20-year data retention subbullet. revision c+1 (april 14, 1999) deleted duplicate sections in the full data sheet. data retention added table. revision d (november 17, 1999) ac characteristics?figure 11. program operations timing and figure 12. chip/sector erase operations deleted t ghwl and changed oe# waveform to start at high. physical dimensions replaced figures with mo re detailed illustrations. revision d+1 (dece mber 5, 2000) added table of contents. ordering information deleted burn-in option. revision d+2 (november 8, 2004) global added cover page, colophon, and referenced links updated trademark. ordering information added temperature range for pb-free packages. valid combinations added new combinations. revision d3 (december 22, 2005) global deleted 120 and 150 ns speed options, and deleted re- verse tsop package option. revision d4 (may 19, 2006) added ?not recommended for new designs? note. ac characteristics changed t busy specification to maximium value. revision d5 (november 2, 2006) deleted ?not recommended for new designs? note. revision d6 (march 5, 2009) global added obsolescence information. revision d7 (august 3, 2009) global removed obsolescence information. revision d8 (november 11, 2009) global removed all commercial temperature range options.
38 am29f032b 21610d8 november 11, 2009 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limita- tion, ordinary industrial use, general o ffice use, personal use, and household use, but are not designed, developed and manufac tured as con- templated (1) for any use that includes fatal risks or dangers th at, unless extremely high safety is secured, could have a seri ous effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolera ble (i.e., submersible repeater and artifici al satellite). please note that spansion inc. will not be liable to you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any se miconductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and pr evention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on expor t under the foreign exchange and foreign trade law of japan, the us export administra tion regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those pr trademarks copyright ? 1998?2005 advanced micro devices, inc. all rights reserv ed. amd, the amd logo, and combinations thereof are registe red trade- marks of advanced micro devices, inc. expressflash is a trademar k of advanced micro devices, inc. product names used in this pu blication are for identification purposes only and may be tr ademarks of their respective companies. copyright ? 2006-2009 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, eco- ram? and combinations thereof, are trademarks and registered tr ademarks of spansion llc in the united states and other countrie s. other names used are for informational purposes only and may be trademarks of their respective owners.

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